This invention relates generally to field programmable gate array (“FPGA”) integrated circuit devices, such as programmable logic devices (“PLDs”), and more particularly to programmable circuitry for measuring the PPM (parts per million) frequency difference between two input clocks and related operating methods for such devices.
PLDs are well-known devices as shown, for example, by such references as Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, Jefferson et al. U.S. Pat. No. 6,215,326, and Ngai et al. U.S. Pat. No. 6,407,576. In general, a PLD is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. PLD technology is well-known for its ability to allow one common hardware design to be programmed to meet the needs of many different applications. Rather than having to design and build separate logic circuits for performing different logic tasks, general-purpose PLDs can be programmed in various different ways to perform those various logic tasks. Many manufacturers of electronic circuitry and systems find PLDs to be an advantageous way to provide system components because they can be manufactured in large quantities at low cost.
The performance of FPGA architectures has increased remarkably in recent years. FPGA integrated circuit devices are now used in a multitude of high-speed applications, such as high-speed serial interfaces (“HSSIs”). These interfaces often process serial input data at rates in excess of 1 Gbps and may additionally recover embedded clock information from these high-speed serial data signals. For example, Lee et al. U.S. Pat. No. 6,650,140, shows a PLD that includes HSSI circuitry that can support several high speed serial (“HSS”) standards. Some of these standards, including the XAUI standard, specify multiple channels of clock data recovery (“CDR”) data. As shown in Aung et al. U.S. Patent Application Publication No. 20010033188, filed Mar. 13, 2001, CDR circuitry may be used to recover an embedded clock signal from a serial data stream by using a reference clock and a feedback clock.
CDR signaling is now being used in many different signaling protocols and applications. These protocols and applications vary with respect to such parameters as clock signal frequency, header configuration, packet size, data word length, number of parallel channels, etc. In addition, these protocols and applications may each specify a different requirement for acceptable PPM frequency threshold between the reference and feedback clocks before data recovery may begin.
Clock frequency detectors, especially PPM threshold detectors, are areas in which it would be highly desirable to have a programmable solution to avoid building specific detectors for the plethora of different applications.